USC and Quantum Elements show surface-code error correction scaling on IBM Heron processors
A Nature Communications paper reports below-threshold logical qubits on hardware whose layout does not match the code, by pairing error correction with dynamical decoupling to tame idle-time noise.
Researchers from Quantum Elements and the University of Southern California have demonstrated surface code error correction scaling on IBM's Heron-generation quantum processors, according to a report by The Quantum Insider on 15 September 2026. The work, published in Nature Communications under the title "Surface code scaling on heavy-hex superconducting quantum processors", was led by Daniel Lidar, chief scientific officer at Quantum Elements and director of USC's Center for Quantum Information Science and Technology, with Quantum Elements research scientist Arian Vezvaee and co-authors at USC.
The surface code is one of the most studied methods of quantum error correction, but it is designed for qubits arranged in a square grid. IBM's Heron processors use a heavy-hex layout, which is more sparsely connected. Mapping the code onto that hardware requires additional routing operations, and those create idle periods during which errors accumulate on waiting qubits.
The team addressed this by combining a depth-efficient version of the surface code with dynamical decoupling, a technique that applies control pulses during idle time to suppress noise. Running on two Heron processors, they report logical qubits that achieved below-threshold performance as the code distance increased. The scaling was directional: when the code grew in one dimension, it became more effective at protecting against the corresponding type of logical error.
The report did not include specific logical error rates. Lidar said hybrid approaches that pair decoupling with error correction will likely continue to outperform either technique on its own in future processors. Quantum Elements says the method underpins Orbit, a Qiskit Function it offers to users of IBM's platform.
Why it matters
Fault-tolerant quantum computing depends on a simple test: adding more physical qubits to a logical qubit must make it better, not worse. Clearing that threshold on hardware whose geometry does not match the code is a meaningful result, because it suggests error correction schemes can be adapted to real processors rather than waiting for processors built to match a textbook layout. It also illustrates a practical truth of the field: progress is coming as much from cleverer control and compilation as from new physics, and the software layer between algorithm and hardware is where much of the engineering now happens.
Fault-tolerant quantum computing depends on a simple test: adding more physical qubits to a logical qubit must make it better, not worse.
Surface code wants a square grid
Each data qubit is checked by neighbours on four sides; the code distance sets how many errors it tolerates.
Heavy-hex offers fewer neighbours
IBM's sparser layout means some checks must be routed through intermediate qubits.
Routing creates idle time
Qubits that wait for routed operations keep decohering, so errors accumulate.
Dynamical decoupling fills the gaps
Pulse sequences applied during idle periods suppress that drift before it becomes an error.
Below-threshold scaling
Larger code distance gave lower logical error, along the direction the code was grown.
What you can learn from this
- A logical qubit is an encoding, not a device. Quantum error correction spreads one unit of quantum information across many physical qubits so that errors on individual qubits can be detected and corrected without measuring, and therefore destroying, the information itself. The surface code does this with data qubits and measurement qubits arranged so that each check involves only a few neighbours. The code distance, roughly the width of the patch, sets how many simultaneous errors the code can tolerate.
- Below threshold is the number that matters. Every physical qubit added introduces more chances for error, so a code only helps if the correction it provides outpaces the noise it adds. Below a certain physical error rate, called the threshold, increasing the code distance makes the logical error rate fall exponentially. Above it, bigger codes get worse. Showing that larger distance produced lower logical error is therefore the milestone, and it is why "as the code distance increased" is the important clause in this result.
- Connectivity is the hidden cost in hardware. The surface code assumes each data qubit can interact directly with four neighbours. Heavy-hex layouts give qubits two or three neighbours, which reduces crosstalk and frequency collisions but means some interactions must be routed through intermediate qubits. Routing costs time, and in superconducting hardware time is noise, because qubits decohere while they wait. Every compiler for real quantum hardware has to manage this trade.
- Dynamical decoupling is noise cancellation for idle qubits. A qubit that is not being operated on still drifts under the influence of its environment. Dynamical decoupling applies carefully timed sequences of pulses that average that drift out, in the same spirit as the spin echo used in magnetic resonance imaging. It does not fix errors that have already happened; it prevents some from happening in the first place. Pairing it with error correction attacks noise at two levels at once, which is the hybrid approach Lidar describes.
- The result was directional, and that is informative. The paper reports that growing the code in one direction improved protection against the corresponding error type. Surface codes protect against bit-flip and phase-flip errors along different axes of the patch, so this behaviour is consistent with the theory. It also signals that hardware noise is not uniform, and that a practical error-corrected processor will likely use rectangular rather than square patches shaped to the noise it actually sees.
We teach this
How to use this in practice
- Build a repetition code in a simulator. Using Qiskit or a similar open framework, encode one qubit across three, apply a random bit-flip to one of them, measure the two parity checks and correct. Then extend it to five qubits and compare failure rates under the same noise model. Done looks like a plot where the five-qubit code fails less often than the three-qubit code at low noise and more often at high noise, which is threshold behaviour in miniature.
- Look at a real coupling map. Fetch the connectivity graph of a Heron-class backend through the IBM Quantum platform, or find a published diagram, and count the neighbours of a few qubits. Then sketch how you would lay a three-by-three surface code patch onto it and mark which interactions would need routing. Done looks like a drawing that shows you exactly where idle time would appear.
- Run a dynamical decoupling experiment on an idle qubit. In a simulator with a realistic noise model, prepare a superposition, wait for a fixed delay, and measure how often it decays. Then insert a simple pair of X pulses during the delay and repeat. Done looks like a measurable improvement in the second case, plus a one-sentence explanation of why the pulses helped.
- Read the abstract and one figure of the paper. Find "Surface code scaling on heavy-hex superconducting quantum processors" in Nature Communications, read the abstract, and pick one figure that plots logical error against code distance. Write down what the axes are and which direction is better. Done looks like being able to explain to someone else, without jargon, why a downward slope on that plot is the whole point.
Sources
- Quantum Elements and USC Demonstrate Surface Code Scaling on IBM Heron — The Quantum Insider
Our reporting is an original summary; full coverage is at the links above.
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