Arm launches Neoverse CSS N4, a 3nm compute subsystem for next-generation server CPUs and DPUs
A pre-built processor design shows how chipmakers now assemble server silicon from licensed blocks rather than starting from scratch.
Arm has released Neoverse CSS N4, a compute subsystem intended as the starting point for the next generation of power-efficient server processors and data processing units, ServeTheHome reported on 9 September. It bundles cores, interconnect, memory controllers and I/O into one pre-integrated block that a chip company can extend with its own accelerators.
The subsystem uses Neoverse N4 cores on the Armv9.3 architecture and scales from 8 to 128 cores per die at clock speeds of up to 3.8 GHz, with FP8 and matrix multiply (MMLA) instructions for inference work on general-purpose CPUs. It is designed for 3nm process nodes. Cores are linked by Arm's CMN S4 interconnect in a mesh of up to 16 by 16, and several dies can be joined into one coherent system over the CHI C2C die-to-die interface.
Memory support covers LPDDR6 as well as DDR5 and multiplexed-rank DIMMs (MRDIMMs) at 8,000 to 12,000 MT/s, and up to 128 lanes of PCIe Gen7 are available for accelerators, storage and networking. Arm positions the design for CPUs, DPUs and network appliances; ServeTheHome cited the XSight Labs E1 DPU, built on the earlier CSS N2, as the kind of product it is meant to succeed. No ship date or benchmark figures were given, and the article describes CSS N4 as aimed at processors at least one generation away.
Why it matters
The compute-subsystem model is how hyperscalers and networking vendors have been getting custom Arm silicon to market quickly. The specification is also a map of server bottlenecks: PCIe Gen7 for accelerator bandwidth, MRDIMMs and LPDDR6 for memory bandwidth per core, and die-to-die coherence because one 3nm die can no longer hold everything a designer wants. One subsystem serving both CPUs and DPUs signals that offloading network and storage work onto dedicated silicon is now standard practice.
The compute-subsystem model is how hyperscalers and networking vendors have been getting custom Arm silicon to market quickly.
Neoverse N4 cores
8 to 128 Armv9.3 cores per die, up to 3.8 GHz, with FP8 and MMLA instructions
CMN S4 mesh interconnect
Up to a 16 by 16 grid tying cores, cache and controllers together
Memory controllers
DDR5 and MRDIMM at 8,000 to 12,000 MT/s, or LPDDR6
I/O
Up to 128 lanes of PCIe Gen7 for accelerators, storage and networking
CHI C2C die-to-die link
Coherent connection so several dies behave as one processor
What you can learn from this
- A compute subsystem is a different product from a core licence. Traditionally Arm sold cores as intellectual property and left customers to design the fabric, memory controllers, I/O and physical layout around them. A CSS bundles those pieces into a pre-validated block already implemented for a specific process node. The customer adds its own accelerators, security blocks and glue logic. The payoff is time: integration and verification are done once by Arm rather than repeated by every licensee, which is why custom server chips have appeared from cloud providers and networking firms that were not previously chip designers.
- Mesh interconnects scale where buses do not. In a mesh, each core or cache slice sits at a grid point and talks to its neighbours, so total bandwidth grows with the size of the grid instead of saturating a single shared channel. The price is that latency depends on how many hops a request takes, so the placement of memory controllers and cache matters. A 16 by 16 mesh is what lets a design span from 8 to 128 cores using the same fabric.
- Die-to-die coherence turns several chips into one machine. As process nodes shrink, very large dies become expensive because a single defect can ruin a lot of silicon and because there is a hard limit on how big a die a lithography tool can print. Splitting the design into smaller dies improves yield. A coherent die-to-die link such as CHI C2C lets every core see one shared memory space, so the operating system treats multiple dies as one processor rather than as separate sockets.
- Memory bandwidth per core is the quiet constraint. Core counts have grown faster than the rate at which a memory channel can deliver data, so many workloads spend time waiting on DRAM. MRDIMMs address this by interleaving two ranks behind a buffer so the channel runs at a higher effective transfer rate, which is how figures like 12,000 MT/s become possible. LPDDR6 offers a different trade: lower power per bit at the cost of capacity and expandability, which suits dense, fixed-configuration systems.
- A DPU is a server for the server. A data processing unit runs the networking, storage and security stack on its own cores so the host CPU is left for applications. It needs many efficient cores, wide PCIe and fast networking rather than peak single-thread speed, which is why the same subsystem can be aimed at both server CPUs and DPUs with different accelerator blocks attached.
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How to use this in practice
- Map the topology of the machine you already have. On Linux, run
lscpuand thenlstopofrom the hwloc package to see cores, cache levels and NUMA nodes as a picture; on Windows, useGet-CimInstance Win32_Processor | Select-Object Name,NumberOfCores,NumberOfLogicalProcessorsand the Task Manager CPU view; on macOS,sysctl -n hw.ncpuandsysctl hw.cachesize. Done is a one-page note listing core count, cache sizes and how many memory nodes the operating system sees, which becomes your reference when you read server specifications. - Measure whether a task is memory-bound or compute-bound. In Python with NumPy, allocate a 2 GB float array and time a streaming operation such as
a.sum(), then time a matrix multiply that touches a similar number of bytes. Divide bytes moved by elapsed seconds to get GB/s for each. Done is two numbers in a notebook and a sentence explaining why the streaming case is limited by memory bandwidth while the multiply is limited by arithmetic throughput. Run it again with a 200 MB array and note how the streaming figure changes once the data fits in cache. - Check the PCIe link your GPU or SSD is actually using. On Linux,
sudo lspci -vv | grep -E "LnkCap|LnkSta"shows the maximum and current link generation and width; with an NVIDIA GPU,nvidia-smi -q | grep -i -A3 "PCIe Generation"does the same. Each PCIe generation roughly doubles the bandwidth of the previous one, so a device negotiated down a generation is losing half its potential. Done is a record of your current link speed and width alongside what Gen7 would provide at the same width. - Draw the CSS N4 block diagram from the specification. Sketch a die with a grid of N4 cores on a mesh, memory controllers along one edge feeding DDR5, MRDIMM or LPDDR6, PCIe Gen7 lanes along another edge, and a CHI C2C link out to a second die. Annotate each block with the figure from the article (8 to 128 cores, 3.8 GHz, 128 lanes, 12,000 MT/s). Done is a labelled diagram you could use to explain why a designer would choose two dies rather than one.
Sources
- Arm Neoverse CSS N4 Launched for Next-Gen CPUs and DPUs — ServeTheHome
Our reporting is an original summary; full coverage is at the links above.
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